1. Field of the Invention
This invention relates to electronic circuits, and more particularly, to an efficient method of repeatable accurate real-time power estimation.
2. Description of the Relevant Art
The power consumption of modern integrated circuits (IC's) has become an increasing design issue with each generation of semiconductor chips. Increased IC power consumption directly affects the cost of building a system. As power consumption increases, more costly cooling systems such as larger fans and heat sinks must be utilized in order to remove excess heat and prevent IC failure. However, cooling systems increase the system cost. The IC power dissipation constraint is not only an issue for portable computers and mobile communication devices, but also for high-performance superscalar microprocessors, which may include multiple processor cores, or cores, and multiple pipelines within a core.
The power consumption of IC's, such as modern complementary metal oxide semiconductor (CMOS) chips, is proportional to the expression αfCV2. The symbol α is the switching factor, or the probability a node will charge up or discharge during a clock cycle. The symbol f is the operational frequency of the chip. The symbol C is the equivalent capacitance, or the switching capacitance, to be charged or discharged in a clock cycle. The symbol V is the operational voltage of the chip. In an attempt to reduce the power consumption of the chip, and to reduce the electrostatic fields within the transistors, the power supply voltage V may be decreased. There is a limit to the power supply voltage reduction, since this reduction decreases the amount of current that may flow through a transistor and, thus, increases the propagation delays through transistors. If the threshold voltages are reduced in order to turn-on the transistors at an earlier time and aid in maintaining performance, then transistor leakage current increases. An increase in transistor leakage current both increases power consumption and the potential for logic failure.
The geometric dimensions of devices and metal routes on each generation of cores are decreasing. Superscalar designs increase the density of integrated circuits on a die with multiple pipelines, larger caches, and more complex logic. Therefore, the number of nodes that may switch per clock cycle significantly increases. Operational frequencies have been increasing with each generation too. The switching factor, α, may decrease for certain blocks or units in the chip by disabling the clock to these areas during periods of non-use. Therefore, although the operational voltage and switching factor may be decreasing with each generation of ICs, the other terms in the IC power consumption expression are increasing and cause an overall increase in power consumption. Some solutions to this power consumption increase include both microarchitectural and circuit-level techniques.
These design techniques are aided by efforts to estimate the power consumption in real-time. For example, while running an application or applications, if the real-time power consumption of a core is both known and conveyed to a power manager, then the power manager may alter the operational supply voltage, the operational frequency, or both in order to increase performance during low power consumption periods, or to decrease power consumption during high power consumption periods.
Real-time power estimation may be achieved by a monitor measuring the switching capacitance on a die during a particular clock cycle. A node capacitance, Cac, comprises both the switched, or ac, capacitance, and the effective capacitance resulting from crossover current. For a given part, leakage current is fixed when operation has reached the temperature limit. This leakage value can be accounted for by a fused-in power offset based on measurements at test time. Attempts to take advantage of temperature induced variations in leakage current is not encouraged due to repeatability reasons discussed below. Therefore, what is needed in order to obtain an accurate real-time estimation of the chip's power is the operational supply voltage, which is set digitally, the operational frequency, which is known, the fused-in leakage value found during testing, and a measurement of the number of nodes in the design switched in a particular clock cycle along with the node capacitance, Cac. The latter term, Cac, is not a straight-forward value to measure on a semiconductor chip.
An on-chip monitor may attempt to measure the switching node capacitance, Cac. The monitor may measure the instruction issue rate within a core or within a processor with multiple cores. Accuracy increases if the behavior of major components such as the instruction issue queue, the reorder buffer, the physical register files, the execution units, and other, and their respective interactions are monitored. However, sampling the hundreds of signals to accomplish this task provides a huge overhead in additional metal routes, increased circuitry, and added power consumption.
Further, a monitor and subsequent response mechanism, such as a power manager, need to be deterministic. In other words, the monitor and mechanism need to provide the same results, or frequency changes, from part-to-part, system-to-system, and run-to-run. The reason for this requirement is Original Equipment Manufacturers (OEMs) using the processor in one of their systems need to provide performance guarantees to customers. Customers and OEMs need to replicate the benchmarks and performance measures at different times and in different locations. If this replication can not be done within a tight tolerance (i.e. +/−1.5%), then the monitor and response mechanism need to be turned off. Now the monitor and mechanism take up area on the die without performing useful work to improve performance and power savings.
Analog sensors, such as temperature sensors and/or an ammeter, are able to provide accurate power estimations, but all of them are environment dependent. Variations in fabrication processes, ambient temperature, power supplies, and the quality of the heat removal solution alter the measurements of analog sensors.
In view of the above, efficient methods and mechanisms for providing an accurate digital real-time power estimation of an IC are desired.